Analog designs are quite different from digital designs from a layout perspective. Unlike a large-scale digital design, an analog design usually has a relatively small scale, i.e., an analog circuit typically has a relatively small die size. However, its physical behavior is very sensitive to the layout geometry, e.g., parasitic coupling effect, small signal transmission, wiring crossovers, etc. Hence, area minimization is usually not a concern for an analog design. A digital designer can leverage mature commercial EDA tools to automate layout generation. However, the existing and popular way to generate an analog layout is far from automatic. The manual, time-consuming, error-prone task highly depends on the layout designer's experience and wit. However, analog design automation has become desirable.
To facilitate the automatic analog layout generation, the designer's expertise can be translated to topological constraints. Three symmetry constraints, i.e., device matching, device mirroring, and device proximity constraints, for analog device placement are proposed in the prior art.
The device matching constraint is created for the devices that can share common gate or should be placed closely. The device mirroring constraint is used on two devices that have to be placed symmetrically to avoid parasitic mismatches. For the devices with the same functionality, the device proximity constraint restricts them to be placed together.
The parasitic mismatch between two devices can be minimized by the device matching constraint, the device mirroring constraint, and the device proximity constraint cited above. For example, if the signal paths going out of and coming into the symmetry constrained modules are not symmetric, mismatches might occur and may cause the circuit failure. Therefore, the constraints cited above are commonly adopted in the analog design automation.
Placement is one of the most important processes in layout synthesis for modern analog and mix-signal circuit designs. It determines all the module positions while minimizing the total design area and wire length while satisfying all the user-specified placement constraints for better circuit performance. Although automatic placement techniques are well developed and commonly used for digital circuits, most analog layout designs are still a manual, time-consuming, and tedious task today. The main reason is that the placement of analog layout synthesis must consider numerous complex constraints to reduce the impacts of mismatches, parasitics, and process variations on circuit performance.
However, most previous works focused on a limited subset of these constraints rather than consider all the constraints simultaneously. Several geometrical constraints handling such as the preplaced constraints can be further improved. Therefore, the present invention proposes a new representation to achieve the time complexity lower bound for module packing, avoid redundant perturbations and speed up the whole simulated annealing process as the new representation can maintain geometrical information in itself.